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1 high performance 1a ldo isl80101 the isl80101 is a low voltage, high current, single output ldo specified at 1a output current. this ldo operates from input voltages of 2.2v to 6v. fixe d output voltage options are available in 1.8v, 2.5v, 3.3v and 5.0v versions. other custom voltage options are av ailable upon request. for the adjustable output version of the isl80101, please refer to the ISL80101-ADJ datasheet. a sub-micron bicmos process is utilized for this product family to deliver the best in class analog performance and overall value. this cmos ldo consumes significantly lower quiescent current as a function of load compared to bipolar ldos, which translates into higher efficien cy and packages with smaller footprints. state of the art internal compensation achieves a very fast load transient response. an external capacitor on the soft-start pin provides an adjustable soft-starting ramp. the enable feature allows the part to be placed into a low quiescent current shutdown mode. a power-good logic output signals a fault condition. table 1 shows the differences between the isl80101 and others in its family: features ? 0.2% initial v out accuracy ?1.8% v out accuracy guaranteed over line, load and t j = -40c to +125c ? very low 130mv dropout voltage at v out = 2.5v ? very fast transient response ?programmable soft-starting ? power-good output ? excellent 58db psrr at 1khz ? current limit protection ?thermal shutdown function ? available in a 10 ld dfn package ? pb-free (rohs compliant) applications ? dsp, fpga and p core power supplies ? noise-sensitive instrumentation systems ? post regulation of switched mode power supplies ? industrial systems ?medical equipment ? telecommunications and networking equipment ?servers ? hard disk drives (hd/hdd) related literature ? see an1592 , ?isl80101 high performance 1a ldo evaluation board user guide? table 1. key differences between family of parts part number programmable i limit i limit (default) adj or fixed v out ISL80101-ADJ no 1.75a adj isl80101 no 1.75a 1.8v, 2.5v, 3.3v, 5.0v isl80101a yes 1.62a adj isl80121-5 yes 0.75a 5.0v figure 1. typical application circuit figure 2. dropout vs load current v in pg enable ss gnd v in 1 2 5 4 7 10 9 6 10k 100k 10f 5.4v 10% 5.0v 1.8% sense isl80101 c ss c out r 3 0.01f 3 10f c in v out v out r pg 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 output current (a) dropout voltage (mv) v out = 2.5v august 31, 2011 fn6931.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2009, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl80101 2 fn6931.1 august 31, 2011 block diagram ordering information reference + soft-start control logic thermal sensor fet driver with current limit - + ea v in en gnd v out + - pg pg adj ss sense part number (notes 1, 3, 4) part marking v out voltage (note 2) temp range (c) package (pb-free) pkg dwg. # isl80101ir18z dzeb 1.8v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80101ir25z dzfb 2.5v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80101ir33z dzgb 3.3v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80101ir50z dzhb 5.0v -40 to +125 10 ld 3x3 dfn l10.3x3 isl80101eval2z evaluation board notes: 1. add ?-t*? for tape and reel. please refer to tb347 for details on reel specifications. 2. for other output voltages, contact intersil marketing. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl80101 . for more information on ms l please see technical brief tb363 .
isl80101 3 fn6931.1 august 31, 2011 pin configurations isl80101 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 v out v out sense pg gnd v in v in nc enable ss epad pin descriptions pin number pin name description 1, 2 v out regulated output voltage. a minimum 10f x5r/x7r output capacitor is required for stability. see ?external capacitor requirements? on page 8 for more details. 3 sense the pgood circuit uses this inpu t to monitor the output voltage status, providing a remote voltage sense. 4 pg this is an open drain logic output used to indicate the status of the output voltage. logic low indicates v out is not in regulation. this pin must be grounded if not used. 5gndground. 6 ss external capacitor on this pin adjusts startup ramp and controls inrush current. 7enable v in independent chip enable. ttl and cmos compatible. 8 nc no connection. leave floating. 9, 10 v in input supply. a minimum of 10f x5r/x7r input capaci tor is required for proper operation. see ?external capacitor requirements? on page 8 for more details. - epad epad at ground potential. it is recommended to solder the epad to the ground plane.
isl80101 4 fn6931.1 august 31, 2011 absolute maximum rating s thermal information v in relative to gnd (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v v out relative to gnd (note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v pg, enable, sense, ss relative to gnd (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v esd rating human body model (tested per jesd22 a114f) . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22 a115c) . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd 78c, class 2, level a) . . . . . 100ma at +85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld dfn package (notes 6, 7) . . . . . . . . 48 7 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions (notes 8, 9) junction temperature range (tj) (note 8) . . . . . . . . . . . .-40c to +125c v in relative to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2v to 6v v out range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mv to 5v pg, enable, sense/adj, ss relative to gnd . . . . . . . . . . . . . . . . 0v to 6v pg sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6v of 1%. 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 8. extended operation at these conditions may compromise reliabi lity. exceeding these limits will result in damage. recommended operating conditions define limits where specifications are guaranteed. 9. electromigration specification defined as lifetime average ju nction temperature of +110c where max rated dc current = lifetime average current. electrical specifications unless otherwise noted, v in = v out + 0.4v, v out = 1.8v, c in = c out = 2.2f, t j = +25c. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?applications infor mation? on page 8 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. parameter symbol test conditions min (note 10) typ max (note 10) units dc characteristics dc output voltage accuracy v out v out + 0.4v < v in < 6v, 0a < i load < 1a -1.8 1.8 % dc input line regulation v out / v in v out + 0.4v < v in < 6v 1 % dc output load regulation v out / i out 0a < i load < 1a, all voltage options -1 % ground pin current i q i load = 0a, 2.2v < v in < 6v 3 5 ma i load = 1a, 2.2v < v in < 6v 5 7 ma ground pin current in shutdown i shdn enable pin = 0.2v, v in = 6v 0.2 12 a dropout voltage (note 11 )v do i load = 1a, v out = 2.5v 130 212 mv output short circuit current ocp v out = 0v, 2.2v < v in < 6v 1.75 a thermal shutdown temperature tsd 2.2v < v in < 6v 160 c thermal shutdown hysteresis (rising threshold) tsdn 2.2v < v in < 6v 30 c ac characteristics input supply ripple rejection psrr f = 1khz, i load = 1a; v in = 2.2v 58 db f = 120hz, i load = 1a; v in = 2.2v 72 db output noise voltage i load = 1a, bw = 10hz < f < 100khz 63 v rms enable pin characteristics turn-on threshold 2.2v < v in < 6v 0.3 0.8 1 v hysteresis (rising threshold) 2.2v < v out + 0.4v < 6v 10 80 200 mv
isl80101 5 fn6931.1 august 31, 2011 enable pin turn-on delay c out = 10f, i load = 1a 100 s enable pin leakage current v in = 6v, enable = 3v 1 a soft-start characteristics ss pin currents (note 11) ipd v in = 3.5v, enable = 0v, ss = 1v 0.5 1 1.3 ma ichg -3.3 -2 -0.8 a pg pin characteristics v out pg flag threshold 75 85 92 %v out v out pg flag hysteresis 4% pg flag low voltage v in = 2.5v, i sink = 500a 100 mv pg flag leakage current v in = 6v, pg = 6v 1 a notes: 10. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise sp ecified. temperature limits established b y characterization and are not production tested. 11. dropout is defined as the difference in supply v in and v out when the output is below its nominal regulation.. electrical specifications unless otherwise noted, v in = v out + 0.4v, v out = 1.8v, c in = c out = 2.2f, t j = +25c. applications must follow thermal guidelines of the package to determine worst case junction temperature. please refer to ?applications infor mation? on page 8 and tech brief tb379 . boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min (note 10) typ max (note 10) units
isl80101 6 fn6931.1 august 31, 2011 typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. figure 3. dropout vs temperature figure 4. v out vs temperature figure 5. output voltage vs supply voltage f igure 6. output voltage vs output current figure 7. ground current vs load current figure 8. ground current vs supply voltage 0 20 40 60 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (c) dropout voltage (mv) v out = 2.5v i out = 1.0a i out = 0.5a i out = 0.1a -1.8 -1.2 -0.6 0 0.6 1.2 1.8 -50 -25 0 25 50 75 100 125 150 junction temperature (c) dv out (%) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0246 supply voltage (v) output voltage (v) 135 +125c +25c -40c -1.8 -1.2 -0.6 0 0.6 1.2 1.8 0 0.25 0.50 0.75 1.00 output current (a) dv out (%) +125c +25c -40c 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 00.20.40.60.81.0 load current (a) ground current (ma) -40c +125c +25c 0 1 2 3 4 5 24 input voltage (v) ground current (ma) 356
isl80101 7 fn6931.1 august 31, 2011 figure 9a. figure 9b. figure 9. load transient response figure 10. current limit vs temperature (v out = 0v) figure 11. enable start-up (css = 2.2nf) figure 12. psrr vs frequency and load current figure 13. psrr vs frequency and output capacitance (i out = 100ma) typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) v in = 5.4v, v out = 5.0v i out = 500ma i out = 10ma time (50s/div) voltage rails at 50mv/div 20s/div i out = 1a i out = 1ma di/dt = 4a/s v in = 3.7v, v out = 3.3v v in = 2.9v, v out = 2.5v v in = 2.5v, v out = 1.8v time (50s/div) voltage rails at 50mv/div 0 0.5 1.0 1.5 2.0 2.5 3.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 junction temperature (c) current (a) 2.2v 6v enable v out (1v/div) ss (1v/div) pg (1v/div) (2v/div) (500s/div) 0ma 100ma 500ma 1a 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m frequency (hz) psrr (db) 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m frequency (hz) psrr (db) c out = 100f c out = 10f
isl80101 8 fn6931.1 august 31, 2011 applications information input voltage requirements the isl80101 is capable of delivering the following fixed output voltages: 1.8v, 2.5v, 3.3v, 5.0v. due to the nature of an ldo, v in must be some margin higher than v out plus dropout at the maximum rated current of the application if active filtering (psrr) is expected from v in to v out . the generous dropout specification of this family of ld os allows applications to design a level of efficiency. enable operation the enable turn-on threshold is typically 800mv with 80mv of hysteresis. an internal pull-up or pull-down resistor to change these values is available upon request. as a result, this pin must not be left floating, and should be tied to v in if not used. a 1k to 10k pull-up resistor is required for applications that use open collector or open drain outputs to control the enable pin. the enable pin may be connected directly to v in for applications with outputs that are always on. power-good operation pg is a logic output that indicates the status of v out and v in . the pg flag is an open-drain nmos that can sink up to 10ma during a fault condition. the pg pin requires an external pull-up resistor typically connected to the v out pin. the pg pin should not be pulled up to a voltage source greater than v in . pg goes low when the output voltage drops below 84% of the nominal output voltage or if the part is disabled. pg functi ons during current limit and thermal shutdown. for applications not using this feature, connect this pin to ground. soft-start operation the soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or ldo enable. this start-up ramp time can be set by adding an external capacitor from the ss pin to ground. an internal 2a current source charges up this c ss and the feedback reference voltage is clamped to the voltage across it. the start-up time is set by equation 1. equation 2 determines the c ss required for a specific start-up in-rush current, where v out is the output voltage, c out is the total capacitance on the output and i inrush is the desired in-rush current. the external capacitor is always discharged to ground at the beginning of start-up or enabling. external capacitor requirements external capacitors are required for proper operation. careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. output capacitor the isl80101 applies state-of-the -art internal compensation to keep the selection of the output capacitor simple for the customer. stable operation over full temperature, v in range, v out range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10f x5r/x7r is used for local bypass on v out . this output capacitor must be connected to the v out and gnd pins of the ldo with pcb traces no longer than 0.5cm. there is a growing trend to use very-low esr multilayer ceramic capacitors (mlcc) because they can support fast load transients and also bypass very high freque ncy noise from other sources. however, the effective capacitance of mlccs drops with applied voltage, age, and temperature. x7r and x5r dieletric ceramic capacitors are strongly recommen ded as they typically maintain a capacitance range within 20% of nominal voltage over full operating ratings of temperature and voltage. figure 14. line transient response figure 15. output noise spectral density typical operating performance unless otherwise noted: v in = 2.2v, v out = 1.8v, c in = c out = 10f, t j = +25c, i l = 0a. (continued) v in = 2.25v time (200s/div) v in = 2.25v v in = 3.8v v in = 2v/div v out = 5mv/div 0.001 0.01 0.1 1 10 10 100 1k 10k 100k 1m 10m frequency (hz) noise (v/ hz) i l = 1a t start c ss x0.5 2 a --------------------- - = (eq. 1) c ss v out xc out x2 a i inrush x0.5v --------------------------------------------- = (eq. 2)
isl80101 9 fn6931.1 august 31, 2011 additional capacitors of any value in ceramic, poscap, alum/tantalum electrolytic types may be placed in parallel to improve psrr at higher frequenc ies and/or load transient ac output voltage tolerances. input capacitor for proper operation, a minimu m capacitance of 10f x5r/x7r is required at the input. this ceramic input capacitor must be connected to the v in and gnd pins of the ldo with pcb traces no longer than 0.5cm. power dissipation and thermals the junction temperature must not exceed the range specified in the ?recommended operating conditions (notes 8, 9)? on page 4. the power dissipation can be calculated by using equation 3: the maximum allowable ju nction temperature, t j(max) and the maximum expected ambi ent temperature, t a(max) determine the maximum allowable power dissipation, as shown in equation 4: ja is the junction-to-ambient thermal resistance. for safe operation, enure that the power dissipation p d , calculated from equation 3, is less than the maximum allowable power dissipation p d(max) . the dfn package uses the copper ar ea on the pcb as a heat-sink. the epad of this package must be soldered to the copper plane (gnd plane) for effective heat dissipation. figure 16 shows a curve for the ja of the dfn package for different copper area sizes. thermal fault protection the power level and the thermal impedance of the package (+45c/w for dfn) determine when the junction temperature exceeds the thermal shutdown temperature. in the event that the die temperature exceeds around +1 60c, the output of the ldo will shut down until the die temperature cools down to about +130c. current limit protection the isl80101 ldo incorporates protection against overcurrent due to any short or overload condition applied to the output pin. the ldo performs as a constant current source when the output current exceeds the current limit threshold noted in the ?electrical specifications? table on page 4. if the short or overload condition is removed from v out , then the output returns to normal voltage regulation mode. in the event of an overload condition, the ldo may begin to cycle on and off due to the die temperature exceeding thermal fault condition and subsequently cooling down after the power device is turned off. p d v in v out ? () i out v in i gnd + = (eq. 3) p dmax () t jmax () t a ? () ja ? = (eq. 4) figure 16. 3mmx3mm-10 pin dfn on 4-layer pcb with thermal vias ja vs epad-mount copper land area on pcb 37 39 41 43 45 47 49 24681012141618202224 epad-mount copper land area on pcb, mm 2 ja c/w
isl80101 10 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6931.1 august 31, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl80101 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil. com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 7/27/11 fn6931.1 added related literature 7/20/11 main change - deleted adjustable output voltage option version from datasheet, now only refers to fixed output voltage option includes removal of all graphics referring to adjustable voltage option. modified page 1 by adding table of key differences, graphics and changes to text page 2 - updated ordering information by: removing adj device isl80101irajz plus eval boards. updated tape and reel note by changing "add "-t" or "tk"?" to "add "t*"?" updated abs max rating and thermal inform ation by adding esd ratings and latchup changed 10 ld dfn tja and tjc from ?45, 4? to ?48, 7? updated dc output voltage accuracy by combining vout options removed feedback pin (adj option only), feedback input current specs removed "(1a version)" from output short circuit current spec removed adjustable in-rush current limit characterist ics and replaced with soft-start characteristics page 5 - electrical spec note changed from "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." to "p arameters with min and/or ma x limits are 100% tested at +25c, unless otherwise specified. temperature li mits established by characterization and are not production tested." complete rewrite of applications information pod l10.3x3 changed note 4 from "dimension b applies..." to "lead width applies..." changed note callout in detail x from 4 to 5 changed height in side view from 0.90 max to 1.00 max added note 4 callout next to lead width in bottom view in land pattern, corrected lead shap e for 4 corner pins to "l" shape (was rectangular and did not match bottom view) 12/21/2009 fn6931.0 initial release.
isl80101 11 fn6931.1 august 31, 2011 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 6, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 1 package 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 outline max (4x) 0.10 ab 4 c m 0.415 0.23 0.35 0.200 2 4

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